TPC - Technical Programme Committee

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DATE 2025 Technical Programme Committee

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Track D: Design Methods and Tools

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Lukas Sekanina, Brno University of Technology, CZ

Topics

D1 System-level design methodologies and high-level synthesis

Chair: Benjamin Carrion Schaefer, The University of Texas at Dallas, US

Co-Chair: John Wickerson, Imperial College London, GB

Topic Members

Yao Chen, National University of Singapore, SG
Steve Dai, NVIDIA, US
Steven Derrien, University of Rennes 1/IRISA, FR
Zhenman Fang, Simon Fraser University, CA
Lorenzo Ferretti, Micron Technology, US
Shane Fleming, AMD, GB
Cong "Callie" Hao, Georgia Institute of Technology, US
Yuko Hara, Tokyo Institute of Technology, JP
Chandan Karfa, Indian Institute of Technology Guwahati, IN
Luciano Lavagno, Politecnico di Torino, IT
Zhe Lin, Sun Yat-sen University, CN
Souradip Sarkar, Cadence Design Systems, DE
Linghao Song, UCLA, US
Nan Wu, George Washington University, US
Wei Zhang, Hong Kong University of Science and Technology, HK

High-level and system-level synthesis techniques; high-level languages for system and behavioural descriptions; system-level models for design and optimization; methods for HW-SW co-design and partitioning; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; control and data flow analysis; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures, including accelerator-rich architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems; high-level synthesis and system-level design for machine-learning applications.

D2 System simulation and validation

Chair: Georg Weissenbacher, Vienna University of Technology, AT

Co-Chair: Tara Ghasempouri, Department of Computer System, Tallinn University of Technology, Estonia, EE

Topic Members

Antonio Arnone, Cadence, IE
Ezio Bartocci, TU Wien, AT
Masahiro Fujita, University of Tokyo, JP
Abdoulaye Gamatie, CNRS LIRMM / University of Montpellier, FR
Roope Kaivola, Intel Corporation, US
Ramesh Karri, NYU, US
Gianluca Martino, TUHH, DE
Prabhat Mishra, University of Florida, US
Sander Stuijk, Eindhoven University of Technology, NL
Sara Vinco, Politecnico di Torino, IT

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques. NOTE: Papers on simulation of analog circuits should target DT4.

D3 Formal methods and verification

Chair: Stefano Quer, Politecnico di Torino, IT

Co-Chair: Rolf Drechsler, University of Bremen/DFKI, DE

Topic Members

Jade Alglave, Arm and University College London, GB
Ivana Černá, Masaryk University, CZ
Maciej Ciesielski, University of Massachusetts Amherst, US
Alessandro Cimatti, Fondazione Bruno Kessler, IT
Luca Geretti, University of Verona, IT
Shilpi Goel, Amazon, US
Susanne Graf, University Grenoble Alpes, CNRS, FR
Daniel Grosse, Johannes Kepler University Linz, AT
Paula Herber, University of Münster, DE
Alan Hu, University of British Columbia, CA
Katell Morin-Allory, TIMA Laboratory, FR
Laurence Pierre, Univ. Grenoble Alpes, TIMA Lab., FR
Anna Slobodova, Intel, US

Formal models of software and hardware systems; formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis; formal methods in emerging technologies.

DT4 Design and test for analog and mixed-signal circuits and systems, and MEMS

Chair: Salvador Mir, CNRS/Univ. Grenoble Alpes/TIMA, FR

Co-Chair: Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT

Topic Members

Engin Afacan, Gebze Technical University, TR
Florence AZAIS, Univ. Montpellier, CNRS, LIRMM, FR
Tiago Balen, UFRGS, BR
Hung-Ming Chen, Institute of Electronics, National Yang Ming Chiao Tung University, TW
William Eisenstadt, University of Florida, US
Maria Helena Fino, Nova University of Lisbon, PT
Estelle Lauga-Larroze, Univ Grenoble Alpes, FR
Piero Malcovati, University of Pavia, IT
Sule Ozev, ASU, US
Fabio Passos, University of Lisbon and INESC-ID, PT
Elisenda Roca, Instituto de Microelectronica de Sevilla, ES
Armin Tajalli, University of Utah, US
Dani Tannir, Lebanese American University, LB

Analog, radio-frequency, mixed-signal, MEMS system and circuit synthesis and optimization; layout and parasitic-aware synthesis; design for manufacturability, yield, reliability; analysis of variability effects; performance modeling; formal, numerical and symbolic simulation methods; topology generation; HW description languages and models of computation; self-healing and self-calibration; test generation, built-in self-test and design for testability; fault modelling, diagnosis and simulation; defect characterization and failure analysis; on-line test and fault tolerance; test metrics.

DT5 Design and test of hardware security primitives

Chair: Mike Hutter, PQShield, AT

Co-Chair: Fatemeh Ganji, Worcester Polytechnic Institute, US

Topic Members

Aydin Aysu, North Carolina State University, US
Samuel Chef, Nanyang Technological University, SG
Lukasz Chmielewski, Masaryk University (Brno, Czechia), CZ
Milos Drutarovsky, Technical University of Kosice, SK
Wieland Fischer, Infineon Technologies, DE
Sylvain Guilley, Secure-IC, FR
Houman Homayoun, University of California Davis, US
Khaza Anuarul Hoque, University of Missouri, US
Xiaolu Hou, Nanyang Technological University, SG
Tuba Kiyan, Technische Universität Berlin, DE
Johann Knechtel, New York University Abu Dhabi, AE
Sandhya Koteshwara, IBM Research, US
Paolo Maistri, TIMA Laboratory, FR
Svetla Petkova-Nikova, KU Leuven, BE
Pascal Sasdrich, Ruhr-Universität Bochum, DE
Sujoy Sinha Roy, TU Graz, AT
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
Rei Ueno, Kyoto University, JP

Hardware security primitives, including (post-quantum) cryptographic circuits; MPC, zero-knowledge proof systems and homomorphic encryption; side-channel countermeasure primitives and analysis (including modelling, verification, and simulation); fault injection countermeasures and attacks; physically unclonable functions (PUF) and true random number generators (TRNG); hardware trojan primitives; AI methods in hardware security and AI hardware; nano security primitives; lightweight crypto primitives

DT6 Design and test of secure systems

Chair: Tobias Schneider, NXP Semiconductors, AT

Co-Chair: Elif Bilge Kavun, University of Passau, DE

Topic Members

Anita Aghaie, Siemens AG, DE
Victor Arribas, Rambus Inc., NL
Josep Balasch, KU Leuven, BE
Davide Bellizia, Telsy, IT
Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
Ileana Buhan, Radboud University, NL
Elke De Mulder, Google, US
Giorgio Di Natale, TIMA - CNRS, FR
Berndt Gammel, Infineon Technologies, DE
Nisha Jacob Kabakci, Fraunhofer AISEC, DE
Osnat Keren, Bar-Ilan University, IL
Johann Knechtel, New York University Abu Dhabi, AE
Yang Li, University of Electro-Communications, JP
Jingqiang Lin, University of Science and Technology of China, CN
Hadi Mardani Kamali, University of Central Florida, US
Soundes Marzougui, STMicroelectronics, BE
Ahmet Can Mert, i2ware Technology, AT
Thorben Moos, UCLouvain, BE
Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
Martin Novotny, Czech Technical University in Prague, CZ
David Oswald, University of Birmingham, GB
Erdinc Ozturk, Intel, GB
Hammond Pearce, University of New South Wales, AU
Christian Pilato, Politecnico di Milano, IT
Francesco Regazzoni, University of Amsterdam and Università della Svizzera italiana, CH
Aein Rezaei Shahmirzadi, PQShield, DE
Samah Saeed, City College of New York, US
Erkay Savas, Sabanci University, TR
Nicolas Sklavos, Computer Engineering and Informatics Department, University of Patras, GR
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
Junko Takahashi, NTT Social Informatics Laboratories, JP
Tolga Yalcin, Qualcomm, US

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

D7 Network on chip and on-chip communication

Chair: Davide Zoni, Politecnico di Milano, IT

Co-Chair: Amlan Ganguly, Rochester Institute of Technology, US

Topic Members

Cristinel Ababei, Marquette University, US
Jose L. Abellan, University of Murcia, ES
Marco Balboni, SiFive, IT
Davide Bertozzi, University of Ferrara, IT
Sujay Deb, IIIT Delhi, IN
Cedric Killian, Universite Jean Monnet, FR
Alejandro Valero, Universidad de Zaragoza, ES
Qiaoyan Yu, University of New Hampshire, US

Architecture, design methodologies, modelling and simulation techniques for intra- and inter-chip interconnects, network-on-chip and on-chip communication infrastructure, including, but not limited to, topology, routers, interfaces, flow control, quality of service, security, reliability, design space exploration frameworks, on-chip communication specifications and programming models for communication-centric design. Contributions from specific applicative domains are welcomed such as interconnects for high-performance computing, in- or near-memory computing, machine-learning, artificial intelligence accelerators. The topic also covers the design of on-chip communication infrastructures with technological constraints (FPGA, interposer/chiplet for 2.5D, 3D, photonics, non-volatile memory, wireless, etc)

D8 Architectural and microarchitectural design

Chair: Leonidas Kosmidis, Barcelona Supercomputing Center (BSC) and Universitat PolitÃ¨cnica de Catalunya (UPC), ES

Co-Chair: Diana Goehringer, TU Dresden, DE

Topic Members

Chloi Alverti, UIUC, US
Fitsum Assamnew Andargie, Addis Ababa University, ET
Eli Bozorgzadeh, Univ. of California, Irvine, US
Francisco J Cazorla, Barcelona Supercomputing Center, ES
Izzat El Hajj, American University of Beirut, LB
Andrea Guerrieri, EPFL and HES-SO, CH
Vasileios Karakostas, University of Athens, GR
Fernanda Kastensmidt, UFRGS, BR
Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR
Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR
Sohan Lal, Technical University of Hamburg, DE
Patricia Lopez Cueva, Thales Alenia Space, FR
Panagiota Nikolaou, University of Central Lancashire, CY
Tanguy Risset, Univ Lyon, INSA Lyon, Inria, CITI, FR
Lucana Santos, European Space Agency, NL
Cristina Silvano, Politecnico di Milano, IT
Sharad Sinha, Indian Institute of Technology (IIT) Goa, IN
Magnus Själander, Norwegian University of Science and Technology, NO
Mladen Slijepcevic, SiFive, FR

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D9 Low-power, energy-efficient and thermal-aware design

Chair: William Fornaciari, Politecnico di Milano - DEIB, IT

Co-Chair: Grace Li Zhang, TU Darmstadt, DE

Topic Members

Carlos Alvarez, UPC, ES
Yu-Guang Chen, National Central University, TW
Yukai Chen, IMEC, BE
Vidya A. Chhabria, Arizona State University, US
Catalin Bogdan Ciobanu, Transilvania University of Brasov, RO
Tsung-Wei Huang, University of Wisconsin at Madison, US
Tohru Ishihara, Nagoya University, JP
Iris Hui-Ru Jiang, National Taiwan University, TW
Rouwaida Kanj, Synopsys/American University of Beirut(on Leave), LB
Taeyoung Kim, Intel Corporation, US
Woojoo Lee, Chung-Ang University, KR
Vojtech Mrazek, Brno University of Technology, CZ
Donghwa Shin, Department of Intelligent Systems, Soongsil University, KR
Cheng Zhuo, Zhejiang University, CN

Theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behaviour. These can be applied to a full range of applications, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centres and cloud computing). Topics of interest include: thermal/power monitors and knobs at circuit level; hardware/software cross-layer optimizations, with emphasis on power modelling and optimization; temperature modelling and prediction; thermal-power-aware optimization; energy-aware design, battery-aware design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems.

D10 Approximate computing

Chair: Daniel Menard, INSA Rennes, FR

Co-Chair: Anca Molnos, CEA-LIST, FR

Topic Members

Mario Barbareschi, University of Naples Federico II, IT
Silviu-Ioan Filip, Inria, FR
Jie Han, University of Alberta, CA
Honglan Jiang, Shanghai Jiao Tong University, CN
Georgios Karakonstantis, University of Thessaly, GR
Oliver Keszocze, Technical University of Denmark, DK
Alexandra Kourfali, EuroHPC Joint Undertaking, LU
Chang Meng, EPFL, CH
Alessandro Savino, Politecnico di Torino, IT
Florian Scheidegger, IBM Research GmbH, CH
Zdenek Vasicek, Brno University of Technology, CZ
Lan Wei, University of Waterloo, CA

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; finite precision arithmetic, inexact operators; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking; design techniques for stochastic computing.

D11 Reconfigurable systems

Chair: Christos Bouganis, Imperial College London, GB

Co-Chair: Dionisios Pnevmatikatos, National Technical University of Athens & ICCS, GR

Topic Members

Georgi Gaydadjiev, Delft University of Technology / Imperial College, NL
Jan Korenek, Brno University of Technology, CZ
Xavier Martorell, Universitat Politècnica de Catalunya, ES
Stefania Perri, University of Calabria - DIMEG, IT
Ioannis Sourdis, Chalmers University of Technology, SE
Sotirios Xydis, National Technical University of Athens, GR
Grace Zgheib, Intel Corporation, US

Reconfigurable computing platforms and architectures; heterogeneous, run-time reconfigurable platforms; reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data centre and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D12 Logical analysis and design

Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT

Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE

Topic Members

Zhufei Chu, Ningbo University, CN
Valentina Ciriani, Universita' degli Studi di Milano, IT
Peeter Ellervee, Tallinn University of Technology, EE
Jie-Hong Roland Jiang, National Taiwan University, TW
Timothy Kam, Intel, US
Natalia Kushik, Télécom SudParis, FR
Giulia Meuli, Synopsys, IT
Shin-ichi Minato, Kyoto University, JP
Jose Monteiro, INESC-ID, Técnico, U Lisboa, PT
Rajeev Murgai, Synopsys India Pvt. Ltd., IN
Andre Reis, UFRGS, BR

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; FPGA synthesis; arithmetic circuits; logic ECO (engineering change order); logic synthesis utilizing AI/ML techniques; interaction between logic synthesis and physical design.

D13 Physical analysis and design

Chair: Matthias Fuegger, CNRS & LMF, ENS Paris-Saclay, FR

Co-Chair: Shao-Yun Fang, National Taiwan University of Science and Technology, TW

Topic Members

Amin Farshidi, Cadence Design Systems, US
Patrick Groeneveld, DAC, US
Yi-chen Lu, Nvidia, US
Rajit Manohar, Yale University, US
Robert Najvirt, TU Wien, AT
Renan Netto, Federal University of Santa Catarina, BR
Andreas Steininger, TU Wien, AT
Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
Wenjian Yu, Tsinghua University, CN

Statistical timing analysis and closure; asynchronous and mixed synchronous/asynchronous circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modelling, behavioural and reduced order modelling; modelling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D14 Emerging design technologies for future computing

Chair: Michael Niemier, University of Notre Dame, US

Co-Chair: Ari Alastalo, VTT, FI

Topic Members

Ihsen Alouani, CSIT, Queen's University Belfast, UK, GB
Salvatore Amoroso, Synopsys Inc, GB
Giovanni Ansaloni, EPFL, CH
Olivia Chen, Tokyo City University, JP
Deliang Fan, Arizona State University, US
Siddharth Joshi, University of Notre Dame, US
Thomas Kämpfe, Fraunhofer IPMS, DE
Asif Ali Khan, TU Dresden, DE
Lauri Koskinen, University of Oulu, FI
Marko Kosunen, Aalto University, FI
Can Li, The University of Hong Kong, HK
Xueqing Li, Tsinghua University, CN
Vasilis Pavlidis, University of Manchester, GB
Jean-Michel Portal, Aix-Marseille University, FR
Vishnu Unnikrishnan, Tampere University, FI
Pascal Vivet, CEA-Leti, FR
Tony Wu, Facebook, US

Modelling, circuit design, HW/SW co-design, and design automation flows for future computing, including: logic devices based on emerging technologies (e.g., spintronics, ferroelectrics, 2D materials, tunnel transistors, coupled oscillators, NEMS, etc.); alternative interconnect technologies (e.g., optical, RF, 3D, 2D materials, spintronics, etc.); monolithic 3D integration (including TSV modelling and design space exploration, etc.).

D15 Emerging design technologies for future memories

Chair: Rajendra Bishnoi, Delft University of Technology,, NL

Co-Chair: Sonal Shreya, Aarhus University, DK

Topic Members

Harshit Agarwal, IIT Jodhpur, IN
Charles Augustine, Intel Circuit Research Lab, US
Laura Bégon-Lours, ETH Zürich, CH
Erika Covi, University of Groningen, NL
Deliang Fan, Arizona State University, US
Farshad Firouzi, ASU, US
Andre Guntoro, Bosch, DE
Piergiulio Mannocci, Politecnico di Milano, IT
Farshad Moradi, Aarhus University, DK
Jongsun Park, Korea University, KR
Guillaume Prenat, Spintec, FR
Fabrizio Riente, Politecnico di Torino, IT
Joachim Rodrigues, Lund University, SE
William Simon, IBM, CH
Stefan Slesazeck, NaMLab gGmbH, DE
Kanishkan Vadivel, IMEC Netherlands, NL
Xueyan Wang, Beihang University, CN
Tianyao Xiao, Sandia National Laboratories, US
Amirreza Yousefzadeh, University of Twente, NL

Modelling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, Computation-in-memory, neuromorphic computing, DNN accelerator, near memory, 3D-integration, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

D16 Design Automation for Quantum Computing

Chair: Ilia Polian, University of Stuttgart, DE

Co-Chair: Carmen G. Almudever, Technical University of Valencia, ES

Topic Members

Andrew W Cross, IBM, US
Swaroop Ghosh, Pennsylvania State University, US
Lingling Lao, National University of Defense Techonology, CN
Siyuan Niu, Lawrence Berkeley National Lab, US
Fabio Sebastiano, Delft University of Technology, NL
YUNONG SHI, AWS Quantum Technologies, US
Robert Wille, Technical University of Munich, DE

Design methodologies and design automation for quantum and hybrid quantum-classical architectures; compilation, mapping and synthesis methods for quantum circuits; design and performance evaluation of NISQ and beyond algorithms and applications; quantum technologies and hardware architectures; simulation, verification, reliability, test, quantum error correction and error mitigation in quantum systems; design of full-stack quantum computing systems and cross-layer methodologies for NISQ and scalable modular architectures; hardware-software co-design; cryo-CMOS control electronics.

Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking design and test methodologies, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems.

Track Chair: Alberto Bosio, University of Lyon, FR

Topics

A1 Power-efficiency and Smart Energy Systems for Sustainable Computing

Chair: Semeen Rehman, TU Wien, AT

Co-Chair: David Novo, CNRS, LIRMM, University of Montpellier, FR

Topic Members

David Castells-Rufas, Universitat Autònoma de Barcelona, ES
Kuan-Hsun Chen, University of Twente, NL
César Fuguet, CEA List, FR
Min Li, Huawei Research Europe, BE
Yehan Ma, Shanghai Jiao Tong University, CN
Orlando Moreira, GrAI Matter Labs, NL
Jisung Park, POSTECH (Pohang University of Science and Technology), KR
Anuj Pathania, University of Amsterdam, NL
Ourania Spantidi, Eastern Michigan University, US
Arun Subramaniyan, Illumina Inc., US
Swagath Venkataramani, IBM T. J. Watson Research Center, US
Bo Wang, SUTD, SG
Georgios Zervakis, University of Patras, GR

Application design experiences and real implementations of power-efficient and smart energy systems (from uW to microgrid) systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems and related Internet-of-things/Cyber-Physical applications for sustainable computing (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centres, and cloud systems).

A2 Smart Society and Digital Wellness

Chair: Graziano Pravadelli, University of Verona, IT

Co-Chair: Tiziana Margaria, University of Limerick and Lero, IE

Topic Members

Daniela De Venuto, Politecnico di Bari, IT
Florenc Demrozi, Department of Electrical Engineering and Computer Science, University of Stavanger, NO
UmaMaheswari Devi, IBM Research - India, IN
Srinivas Katkoori, University of South Florida, US
Velu Kumaravel, University of Oldenburg, DE
Bo Wen, IBM Research, US
Farhana Zulkernine, School of Computing, Queen's University, CA

Design experiences, practical applications, optimization, and real-life implementations of software, devices, systems, and services, from the Edge to the Cloud, for smart cities, smart homes and people wellness, based on mass market electronics, Internet of Things (IoT), Internet of Medical Things (IoMT), and Internet-of-Everything (IoE). This encompasses a diverse array of subjects, ranging from the development and deployment of advanced technologies to their seamless integration into modern everyday life by means of a variety of AI-powered smart devices and intelligent systems with sensing and acting capabilities, which are adopted in different sectors: from individual’s social care and healthcare to home automation and management of urban infrastructures. Topics of interests include, but are not limited to, the design, the optimization and the application of sensors, sensor networks, wearables, smart devices, cyberphysical and robotic systems for smart home, smart cities, and people wellness, including augmented and assisted living, social care products, healthcare devices, technologies and services for disease’s prevention, diagnosis, treatment and rehabilitation, smart transportation, environmental monitoring, resources’ supply and management (e.g., water, air, energy, etc.), lighting, street cleaning, disposal facilities, etc. including also the use of security-privacy techniques and blockchain technology, 5G and 6G mobile communications, networking devices, audio and video technologies, and advanced human-machine interfaces.

A3 Secure Systems, Circuits and Architectures

Chair: Cedric Marchand, Ecole centrale Lyon, FR

Co-Chair: Mirjana Stojilovic, EPFL, CH

Topic Members

M. Khurram Bhatti, Information Technology University (ITU), PK
Noemie Boher, Intrinsic-ID, NL
Luca Cassano, Politecnico di Milano, IT
Julien Francq, Naval Group, FR
Matthias Hiller, Fraunhofer AISEC, DE
Wei Hu, Northwestern Polytechnical University, CN
Naghmeh Karimi, University of Maryland Baltimore County, US
Cuauhtemoc Mancillas, Cinvestav, MX
Angelos Marnerides, University of Cyprus, CY
Maria Méndez Real, IETR UMR CNRS 6164 Nantes Université, FR
Michael Pehl, Technical University of Munich, DE
Amin Rezaei, California State University, Long Beach, US
Dustin Richmond, University of Washington, US
Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
Jo Vliegen, ES&S, imec-COSIC, ESAT, KU Leuven, BE
QIAN WANG, University of California Merced, US

Secure systems, circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; hardware/software implementations architectures for post quantum embedded cryptography (e.g., post-quantum, lightweight, homomorphic); emerging technologies for secure systems, circuits and architectures; novel architectures for embedded cryptography; demonstrations of fault or other physical attacks (e.g., fault, side-channel) and countermeasures; embedded processors or co-processors for security; protection of off-chip memories, and Network-on-Chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A4 Autonomous Systems and Smart Industry

Chair: Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR

Co-Chair: Lulu Chan, NXP Semiconductors, NL

Topic Members

Donkyu Baek, Chungbuk National University, KR
Domenico Balsamo, Newcastle University, GB
Franco Fummi, University of Verona, IT
Seonyeong Heo, Kyung Hee University, KR
Heba Khdr, Karlsruhe Institute of Technology (KIT), DE
Geoff Merrett, University of Southampton, GB
Antonio Miele, Politecnico di Milano, IT
Paolo Pazzaglia, Robert Bosch GmbH, DE
Amit Kumar Singh, University of Essex, GB

This topic focuses on self-adaptive, learning and/or context-aware systems with run-time decision-making for smart sensing/acting and efficient computing/communication. It targets the compute continuum, covering high-performance compute nodes, power-constrained IoT/edge devices, reconfigurable systems, and heterogeneous/collaborative platforms. Optimization goals involve computing performance, energy/power, reliability, temperature, aging, or quality. Topics of interest include but are not limited to: Adaptive strategies for run-time resource management; Prediction/forecasting and control of self-adaptive systems; Systems and/or algorithms that can adapt their operation based on available resources and context; Data mining, modeling, and optimization techniques for adaptive systems (e.g. control automation and game theory.); Automotive; Autonomous Driving; Mobile Robotics; Human-Robot collaborations in smart factories; Industry 4.0 and 5.0; Digital Twins; Virtualization; Metaverse; 5G/6G; MEMS; Integrated sensors and transducers; Design experiences and industrial use-cases of self-adaptive systems.

A5 Applications of Emerging Technologies

Chair: Mariagrazia Graziano, Politecnico di Torino, IT

Co-Chair: Sébastien Le Beux, Concordia University, CA

Topic Members

Guillermo Botella, Complutense University of Madrid, ES
Kerem Camsari, University of California, Santa Barbara, US
Anupam Chattopadhyay, Nanyang Technological University, SG
Yuanqing Cheng, Beihang University, CN
Luca Gnoli, CNR-ISMN (Institute for the study of nanostructured materials), IT
Said Hamdioui, Delft University of Technology, NL
Bing Li, Technical University of Munich, DE
Alberto Marchisio, New York University Abu Dhabi (NYUAD), AE
M. Hassan Najafi, Case Western Reserve University, US
Stefania Perri, University of Calabria - DIMEG, IT
Luca Pezzarossa, Technical University of Denmark, DK
Azzurra Pulimeno, Camlin Group, IT
Frank Sill Torres, German Aerospace Center, DE
Himanshu Thapliyal, University of Tennessee, US
Elena Ioana Vatajelu, TIMA, FR
Shigeru Yamashita, Ritsumeikan University, JP
Xunzhao Yin, Zhejiang University, CN

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A6 Applications of Artificial Intelligence Systems

Chair: Stylianos Venieris, Samsung AI, GB

Co-Chair: Christos Kyrkou, KIOS CoE, University of Cyprus, CY

Topic Members

Javier Fernandez-Marques, Flower Labs, GB
Alexandros Kouris, Samsung AI and Imperial College London, GB
Stefanos Laskaridis, Samsung AI Center Cambridge, GB
Kleanthis Malialis, University of Cyprus, CY
Ioannis Papaefstathiou, Aristotle University of Thessaloniki, GR
Tommaso Polonelli, ETH Zürich, CH
Qing Wang, Delft University of Technology, NL
Shuochao Yao, George Mason University, US

Advanced technologies and systems, software, algorithmic and co-design approaches and optimizations for artificial intelligence (AI), machine learning and deep learning solutions for domain-specific applications in the context of computing continuum and embodied AI: from resource-constrained edge devices (for example machine learning on microcontrollers and low-power processors embedded in mobile and/or autonomous systems) up to high-performance computing in the cloud and their applications. Topics of interests include Computer Vision, Natural Language Processing, Generative AI, Large Language Models, Large Vision Models, Vision-Language Models, Few-Shot Learning, Continual Learning, Distributed and Federated AI, Robust AI, Real-Time and Adaptive Inference, Quantization and Pruning, Neural Architecture Search.

Track T: Test and Dependability

covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Matteo Sonza Reorda, Politecnico di Torino, IT

Topics

T1 Modeling and mitigation of defects, faults, variability, and reliability

Chair: Leticia Maria Bolzani Poehls, RWTH Aachen University, DE

Co-Chair: Mottaqiallah Taouil, Delft University of Technology, NL

Topic Members

Hussam Amrouch, Technical University of Munich (TUM), DE
Davide Appello, Technoprobe, IT
Daniel Arumi, UPC, ES
Sarah Azimi, Politecnico di Torino, IT
Riccardo Cantoro, Politecnico di Torino, IT
Bram Kruseman, NXP Semiconductors, NL
Huawei Li, Institute of Computing Technology, Chinese Academy of Sciences, CN
Cristina Meinhardt, UFSC, BR
Jaan Raik, Tallinn University of Technology, EE
Christian Sauer, Synopsys, DE
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
Arnaud Virazel, LIRMM, FR
Hank Walker, Texas A&M University, US

Identification, characterization, and modelling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability assessment and modelling at device, circuit, or system level; process yield modelling and enhancement; design-for-manufacturability, design-for-yield and design-for-reliability; noise and uncertainty modelling at device or circuit level; modelling and mitigation of physical sources of faults and errors such as process, voltage, temperature and temporal variations at device or circuit level.

T2 Test generation, test architectures, design for test, and diagnosis

Chair: Sybille Hellebrand, University of Paderborn, DE

Co-Chair: Jerzy Tyszer, Poznan University of Technology, PL

Topic Members

Paolo Bernardi, Politecnico di Torino, IT
Jennifer Dworak, Southern Methodist University, US
Stephan Eggersgluess, Siemens EDA, DE
Stefan Holst, Kyushu Institute of Technology, JP
Yu Huang, HiSilicon, US
Maksim Jenihhin, Tallinn University of Technology, EE
Chrysovalantis Kavousianos, Department of Computer Science and Engineering, University of Ioannina, GR
Artur Pogiel, Siemens Digital Industries Software, PL
Annachiara Ruospo, Politecnico di Torino, IT
Melanie Schillinsky, NXP Germany GmbH, DE
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT

Automated test pattern generation targeting basic and advanced fault models (timing-related, defect-based, cell-aware) in a wide range of semiconductor digital integrated circuits including microprocessors, SoC, FPGAs, memories, NoCs, accelerators, hardware for machine learning and artificial intelligence, 2.5D and 3D architectures; silent data corruption; fault simulation; power and thermal issues in test; design for testability (DFT); test compression; multi-corner stress tests; volume fault diagnosis and yield analysis; logic built-in self-test (BIST) and memory BIST; in-system test; board and system-level test; test scheduling; machine learning and artificial intelligence in IC testing.

T3 Dependability and system-level test

Chair: Dimitris Gizopoulos, University of Athens, GR

Co-Chair: Osman Unsal, Barcelona supercomputing center, ES

Topic Members

Cristiana Bolchini, Politecnico di Milano, IT
Stefano Di Carlo, Politecnico di Torino, IT
Harish Dixit, Meta Platforms Inc., US
Sudhanva Gurumurthi, Advanced Micro Devices, Inc (AMD), US
Siva Kumar Sastry Hari, NVIDIA, US
Jiun-Lang Huang, National Taiwan University, TW
David Kaeli, Northeastern University, US
Yanjing Li, University of Chicago, US
Cameron McNairy, Tenstorrent, US

Dependability evaluation and enhancement solutions crossing all layers of the computing system’s stack including but not limited to: microarchitecture-level, architecture-level, software-level, and system-level; fault and error modelling; cross-layer dependability analysis, evaluation, and improvements; reliable and fail-safe architectures and systems design; system-level on-line test and functional safety; runtime system management for dependability; application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level and microarchitecture-level solutions for safety- and mission-critical systems; large-scale computing dependability and emerging failure modes, silent data corruptions at scale (cloud, HPC, edge, IoT).

DT4 Design and test for analog and mixed-signal circuits and systems, and MEMS

Chair: Salvador Mir, CNRS/Univ. Grenoble Alpes/TIMA, FR

Co-Chair: Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico – Universidade de Lisboa, PT

Topic Members

Engin Afacan, Gebze Technical University, TR
Florence AZAIS, Univ. Montpellier, CNRS, LIRMM, FR
Tiago Balen, UFRGS, BR
Hung-Ming Chen, Institute of Electronics, National Yang Ming Chiao Tung University, TW
William Eisenstadt, University of Florida, US
Maria Helena Fino, Nova University of Lisbon, PT
Estelle Lauga-Larroze, Univ Grenoble Alpes, FR
Piero Malcovati, University of Pavia, IT
Sule Ozev, ASU, US
Fabio Passos, University of Lisbon and INESC-ID, PT
Elisenda Roca, Instituto de Microelectronica de Sevilla, ES
Armin Tajalli, University of Utah, US
Dani Tannir, Lebanese American University, LB

DT5 Design and test of hardware security primitives

Chair: Mike Hutter, PQShield, AT

Co-Chair: Fatemeh Ganji, Worcester Polytechnic Institute, US

Topic Members

Aydin Aysu, North Carolina State University, US
Samuel Chef, Nanyang Technological University, SG
Lukasz Chmielewski, Masaryk University (Brno, Czechia), CZ
Milos Drutarovsky, Technical University of Kosice, SK
Wieland Fischer, Infineon Technologies, DE
Sylvain Guilley, Secure-IC, FR
Houman Homayoun, University of California Davis, US
Khaza Anuarul Hoque, University of Missouri, US
Xiaolu Hou, Nanyang Technological University, SG
Tuba Kiyan, Technische Universität Berlin, DE
Johann Knechtel, New York University Abu Dhabi, AE
Sandhya Koteshwara, IBM Research, US
Paolo Maistri, TIMA Laboratory, FR
Svetla Petkova-Nikova, KU Leuven, BE
Pascal Sasdrich, Ruhr-Universität Bochum, DE
Sujoy Sinha Roy, TU Graz, AT
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
Rei Ueno, Kyoto University, JP

DT6 Design and test of secure systems

Chair: Tobias Schneider, NXP Semiconductors, AT

Co-Chair: Elif Bilge Kavun, University of Passau, DE

Topic Members

Anita Aghaie, Siemens AG, DE
Victor Arribas, Rambus Inc., NL
Josep Balasch, KU Leuven, BE
Davide Bellizia, Telsy, IT
Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
Ileana Buhan, Radboud University, NL
Elke De Mulder, Google, US
Giorgio Di Natale, TIMA - CNRS, FR
Berndt Gammel, Infineon Technologies, DE
Nisha Jacob Kabakci, Fraunhofer AISEC, DE
Osnat Keren, Bar-Ilan University, IL
Johann Knechtel, New York University Abu Dhabi, AE
Yang Li, University of Electro-Communications, JP
Jingqiang Lin, University of Science and Technology of China, CN
Hadi Mardani Kamali, University of Central Florida, US
Soundes Marzougui, STMicroelectronics, BE
Ahmet Can Mert, i2ware Technology, AT
Thorben Moos, UCLouvain, BE
Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
Martin Novotny, Czech Technical University in Prague, CZ
David Oswald, University of Birmingham, GB
Erdinc Ozturk, Intel, GB
Hammond Pearce, University of New South Wales, AU
Christian Pilato, Politecnico di Milano, IT
Francesco Regazzoni, University of Amsterdam and Università della Svizzera italiana, CH
Aein Rezaei Shahmirzadi, PQShield, DE
Samah Saeed, City College of New York, US
Erkay Savas, Sabanci University, TR
Nicolas Sklavos, Computer Engineering and Informatics Department, University of Patras, GR
Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
Junko Takahashi, NTT Social Informatics Laboratories, JP
Tolga Yalcin, Qualcomm, US

Track E: Embedded Systems Design

is devoted to the modelling, analysis, design, verification and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments for real-time systems, cyber-physical systems, networked systems, and dependable systems. Emphasis is, also, on model-based design and verification, embedded software platforms, software compilation and integration for these systems.

Track Chair: Nele Mentens, KU Leuven, BE / Leiden University, NL

Topics

E1 Embedded software architecture, compilers and tool chains

Chair: Ahmed Rezine, Linköping University, SE

Co-Chair: Linh Thi Xuan Phan, University of Pennsylvania, US

Topic Members

Timothy Bourke, Inria / ENS, FR
David Broman, KTH Royal Institute of Technology, SE
Jeronimo Castrillon, TU Dresden, DE
Hsiang-Yun Cheng, Academia Sinica, TW
Joseph Devietti, University of Pennsylvania, US
Soumyajit Dey, IIT Kharagpur, IN
Nan Guan, City University of Hong Kong, HK
Ramkumar Jayaseelan, Meta, US
Michele Lora, University of Verona, IT
Hiren Patel, University of Waterloo, CA
Sara Royuela, Barcelona Supercomputing Center, ES
Konstantinos Sagonas, Uppsala University & Nat. Tech. Univ, of Athens, SE
Soheil Samii, Linköping University, SE
Yi Wang, Shenzhen University, CN

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E2 Real-time, dependable and privacy-enhanced systems

Chair: Jing Li, New Jersey Institute of Technology, US

Co-Chair: Matthias Becker, KTH Royal Institute of Technology, SE

Topic Members

Yasmina ABDEDDAIM, Univ Gustave Eiffel, CNRS, LIGM, FR
Mohammad Ashjaei, Mälardalen University, SE
Nan Chen, University of York, GB
Emmanuel Grolleau, LIAS, ISAE-ENSMA, Universite de Poitiers, FR
Tanja Harbaum, KIT, DE
Sena Hounsinou, Metro State University, US
Tingting Hu, University of Luxembourg, LU
Zhe Jiang, South East University, CN
Nele Mentens, KU Leuven, BE
Behnaz Ranjbar, Ruhr University Bochum, DE
Federico Reghenzani, Politecnico di Milano, IT
Peter Ulbrich, Technische Universität Dortmund, DE

Real-time performance modelling, analysis and empirical evaluation; worst-case performance analysis techniques; WCET analyses, real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time, networked and dependable systems; adaptive real-time systems; dependable real-time systems including fault-tolerance and criticality; timing analysis of security attack protection and privacy-enhancement in time-critical systems; network control and QoS for embedded applications; resource allocation and design-space exploration for real-time embedded systems.

E3 Machine learning solutions for embedded and cyber-physical systems

Chair: Francesco Conti, University of Bologna, IT

Co-Chair: Irem Boybat, IBM Research Europe - Zurich, CH

Topic Members

Elnaz Ansari, Meta, US
Mladen Berekovic, Universität zu Lübeck, DE
Oliver Bringmann, University of Tuebingen / FZI, DE
Alessio Burrello, Politecnico di Torino and UniversitÃ di Bologna, IT
Carmine Cappetta, STMicroelectronics, IT
Anup Das, Drexel University, US
Kaoutar El Maghraoui, IBM, US
Angelo Garofalo, University of Bologna, IT
Maryam Hemmati, University of Auckland, NZ
Daniele Jahier Pagliari, Politecnico di Torino, IT
Axel Jantsch, TU Wien, AT
Eiman Kanjo, Imperial College London, GB
Minkyu Kim, Qualcomm, US
Gokul Krishnan, Apple, US
Hyoukjun Kwon, University of California, Irvine, US
Charles Mackin, IBM Research, US
Nele Mentens, KU Leuven, BE
Andres Otero, Universidad Politecnica de Madrid, ES
Hamza Ouarnoughi, INSA Hauts-de-France, FR
Işıl Öz, Izmir Institute of Technology, TR
Guilherme Paim, KU Leuven, BE
Daniele Palossi, ETH - Zurich, CH
Gianna Paulin, Axelera AI, CH
Fernando Garcia Redondo, imec, GB
Manuele Rusci, KU Leuven, BE
Mohammad Sadrosadati, Sharif University of Technology, IR
Antonis Savva, KIOS Research and Innovation Centre of Excellence, University of Cyprus, CY
Jiawei Xu, KTH Royal Institute of Technology, SE
Amirreza Yousefzadeh, University of Twente, NL
Marina Zapater, University of Applied Sciences Western Switzerland (HES-SO), CH
Lirong Zheng, Fudan University, CN
Guanwen Zhong, AMD Research and Advanced Development (RAD), SG

Hardware architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning solutions; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; case studies of machine learning applications implemented on embedded systems and cyber physical systems.

E4 Design methodologies for machine learning architectures

Chair: Smail Niar, Université Polytechnique and INSA Hauts-de-France and CNRS, FR

Co-Chair: Priyadarshini Panda, Yale University, US

Topic Members

Hadjer Benmeziane, IBM Research, CH
Halima Bouzidi, University of California, Irvine, US
José Cano, University of Glasgow, GB
Henk Corporaal, TU/e (Eindhoven University of Technology), NL
Gourav Datta, Amazon, US
Giorgos Dimitrakopoulos, Democritus University of Thrace, GR
Jana Doppa, Washington State University, US
Fernando Fernandes dos Santos, INRIA, FR
Souvik Kundu, Intel Labs, US
Steven Latre, University of Antwerp - IMEC, BE
Jinho Lee, Seoul National University, KR
Umit Ogras, University of Wisconsin - Madison, US
Ozcan Ozturk, Sabanci University, TR
Mazen Saghir, American University of Beirut, LB
Papaioannou Savvas, University of Cyprus, CY
Jae-sun Seo, Cornell Tech, US
Muhammad Shafique, New York University Abu Dhabi (NYUAD), AE
Marian Verhelst, KU Leuven, BE

Design methodologies, optimizations, verification, analysis and reliability for machine learning architectures; Specializations, and resource-efficient optimizations for machine learning architectures; Embedded architectures and software for autonomy, automated reasoning, and planning algorithms; Approximate architectures for machine learning applications; Learning from limited data sets; Frameworks for probabilistic and deep learning programming; Safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; In-memory and near-memory architectures design for ML; Hyperdimensional computing architectures and ML applications; Quantum computing for ML; Co-design space exploration for ML applications.

E5 Design, specification, modeling and verification for embedded and cyber-physical systems

Chair: Patricia Derler, PARC, US

Co-Chair: Julio Medina, University of Cantabria, ES

Topic Members

Luis Almeida, University of Porto, PT
Grzegorz Bazydło, University of Zielona Góra, PL
Chadlia Jerad, University of Manouba, TN
Chung-Wei Lin, National Taiwan University, TW
Vittoriano Muttillo, University of Teramo, IT
Gianluca Palermo, Politecnico di Milano, IT
Georgios L. Stavrinides, KIOS Research and Innovation Center of Excellence, University of Cyprus, CY
Todor Stefanov, Leiden University, NL

Modelling, design, verification, validation and optimization of complex, heterogeneous, distributed Cyber-Physical Systems (CPS); specification and analysis of functional and non-functional properties, including performance, timing, memory usage, quality-of-service, safety and reliability; meta-models and models of computation, communication, and concurrency for complex HW-SW systems and components of CPS; theories, standards, languages and tools supporting model-based design flows covering software, control, and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining, autonomy, and adaptivity in CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behaviour in smart grids); predictive and learning-based models for CPS.