Multiple research vectors represent possible paths to improved energy and performance metrics at the application-level. There are active efforts with respect to emerging logic devices, new memory technologies, novel interconnects, and heterogeneous integration architectures. Of great interest is quantifying the potential impact of a given solution to prioritize research vectors accordingly.  Ideally, any such comparisons should be made to state-of-the-art/scaled CMOS solutions in an application-level context.  In this presentation, students from SUPREME PI Michael Niemier’s group consider how ferroelectric-based associative memories may be employed for different workloads, and present layout-based analysis to show how said solutions may ultimately compare to highly scaled CMOS solutions across different figures of merit.  Directions and suggestions for future efforts at the algorithmic, layout/chip-design, and materials science-levels – to derive maximum benefits from technology – will also be briefly discussed.

Non-volatile ferroelectric capacitor (nvCap) that leverages the small-signal non-destructive read is a new concept to the ferroelectric memory family. nvCap overcomes the endurance limitation imposed by the destructive read in conventional ferroelectric random access memory (FeRAM) that relies on large-signal polarization switching.  nvCap is also a promising candidate to enable the charge domain computation in a capacitive crossbar array for in-memory computing that only consumes dynamic power.  The key engineering goal of nvCap is to optimize a asymmetric C-V characteristics to open up the large capacitance on/off ratio at DC zero voltage. In this talk, we present the progresses of our work on optimizing the nvCap device. We first introduce the HZO-based MFM nvCap that demonstrates the proof-of-concept, and present the FeFET-based MFS nvCap that improves capacitance on/off ratio with reliability/scaling analysis. Finally we report our new results on BEOL-compatible MFS nvCap based on a oxide semiconductor layer. 
 

This talk introduces the possibility of charge-domain computing using a 1FeFET-1Capacitance (1F1C) macro based on a 2-bit ferroelectric field-effect transistor (FeFET). This cell operating in the charge domain is marking a significant advancement for compute-in-memory (CIM) which improves the energy efficiency but also robustness due to the low capacitor mismatch. Traditionally, NVMs, such as FeFETs or resistive RAMs (RRAMs), have operated in a single-bit fashion, limiting their computational density and throughput. In contrast, the proposed 2-bit FeFET cell enables higher storage density and improves the computational efficiency in CIM architectures. The macro achieves 111.6 TOPS/W, highlighting its energy efficiency, and demonstrates robust performance on the CIFAR-10 dataset, achieving 89% accuracy with a VGG-8 neural network. These findings underscore the potential of charge-domain, multilevel NVM cells in pushing the boundaries of artificial intelligence (AI) acceleration and energy-efficient computing.

Compute-in-Memory (CIM) is a promising non-von Neumann computing paradigm that promises unprecedented improvements in performance and energy efficiency. Moving past manual designs, automation will be key to unleash the potential of CIM for multiple application domains and to accelerate cross-layer design cycles. This talks reports on an ongoing effort to build a high-level compiler infrastructure for different CIM approaches, built with MLIR to abstract from individual technologies to foster re-use. This includes abstractions and optimizations flows for logic-in memory, content-addressable memories, arithmetic operations in crossbars, and near-memory architectures. We also report on recent results retargeting the compiler for novel ferroelectric cells, exploring different memory modalities.